FIG. 7(a) is a plan view showing one pixel of a conventional TFT array substrate, FIG. 7(b) is a plan view showing a TFT portion as a switching element, and FIG. 7(c) is a sectional view taken along line D–D′ in FIG. 7(b). In the figures, reference numeral 1 denotes a transparent insulative substrate; 2, a plurality of gate lines formed on the transparent insulative substrate 1 and gate electrodes provided in the gate lines; 3, a plurality of source lines that have source electrodes 7 and cross the gate lines 2; and 5, a semiconductor layer formed on each gate electrode 2 with a gate insulating film 4 interposed in between. A source electrode 7 and a drain electrode 6 that are connected to the semiconductor layer 5 constitute a TFT. Reference numeral 8 denotes a pixel electrode that is a transparent conductive film and is connected to the drain electrode 6 through a contact hole 10 that is formed through an interlayer insulating film 9. Reference numeral 11 represents a channel width.
A manufacturing method of the conventional TFT array substrate will be described below briefly. Firstly, a metal film of Cr or the like is deposited on a transparent insulative substrate 1 by sputtering method or the like and then patterned by photolithography method or the like, whereby gate lines 2 including gate electrodes are formed. Then, a gate insulating film 4 and a semiconductor layer 5 are deposited consecutively by plasma CVD method or the like. After semiconductor layers 5 are patterned, a metal film is deposited and drain electrodes 6, source electrodes 7, and source lines 3 are formed. Then, an interlayer insulating film 9 made of silicon nitride or the like is formed so as to cover the TFTs. After contact holes 10 are formed, pixel electrodes 8 that are transparent conductive films made of ITO or the like are formed by sputtering method or the like. A TFT array substrate is thus completed.
A liquid crystal display device performs video display by controlling a liquid crystal interposed between the above-described TFT array substrate and a counter electrode substrate according to voltages that are applied between the pixel electrodes 8 on the array substrate and the counter electrode. In this case, if the voltages applied to the pixel electrodes 8 vary in the display area, display defects such as luminance unevenness, shot unevenness, a flicker, etc. may occur.
FIG. 8 shows a relationship between a pixel electrode voltage and each signal voltage. In the figure, reference character A denotes a gate electrode voltage, B denotes a pixel electrode voltage, and C denotes a source electrode voltage. In a charging period CP in which the gate electrode voltage A turns on the TFT, the pixel electrode voltage B is applied to the source electrode 7 and transmitted to the pixel electrode 8 via the drain electrode 6. The pixel electrode voltage Breaches the source electrode voltage C in the charging period CP. However, when the gate electrode voltage A turns off as a transition occurs from the charging period CP to a holding period HP, the pixel electrode voltage B lowers due to capacitance coupling etc. This voltage drop at the pixel electrode 8 is a feedthrough voltage D, which is expressed by the following equation in a simplified manner. In the equation, ΔVgd is a feedthrough voltage, Cgd is a parasitic capacitance between the gate electrode and the drain electrode, Cs is an auxiliary capacitance of the pixel electrode, and Clc is a liquid crystal capacitance.ΔVgd=ΔV×Cgd/(Clc+Cs+Cgd)
One of factors of varying the feedthrough voltage in the display area is a variation of the parasitic capacitance (hereinafter referred to as Cgd) between the gate electrode 2 and the drain electrode 6. In the array substrate in which the pixels and the TFTs are arranged in matrix form, each pattern is formed by photolithography method and one manufacturing step is completed by using a plurality of shots. If an alignment error occurs in each shot in a photolithography apparatus, the pattern arrangement relationships among the gate electrode 2, the semiconductor layer 5, the source electrode 7, the drain electrode 6, etc. vary from one shot to another. Therefore, Cgd which is determined by the overlap area of the gate electrode 2 and the drain electrode 6 varies from one shot to another. As a result, the feedthrough voltage varies from one shot to another and shot unevenness, a flicker, etc. become easy to recognize visually. Further, a portion of the semiconductor layer 5 that is located over the gate line 2 and is located outside the drain electrode 6 is kept at the same potential as the potential of the drain electrode 6 until the gate electrode voltage A turns off. This also contributes to the Cgd variation.
In the conventional TFT structure shown in FIG. 7, alignment errors in the direction parallel with the channel width 11 direction of the TFT cause only small variations in the areas of overlap between the gate line 2, the drain electrode 6, and the semiconductor layer 5. However, there is a problem that no consideration is given to alignment errors in the direction perpendicular to the channel width 11 and such alignment errors cause large variations in areas. Further, in the conventional structure, the load capacitance of the gate line 2 is large. It is desired to decrease it.
Japanese laid Opened Patent Publication No. Hei. 2-10331, for example, proposes a TFT array substrate in which that part of a drain electrode which is formed, with a gate insulating film interposed in between, on a step portion that is formed by the presence of a gate electrode is made narrower than the other portion of the drain electrode, to thereby prevent short-circuiting between layers arranged in the vertical direction that would otherwise occur due to the presence of the step portion. However, this publication has no disclosure relating to the width of a semiconductor layer on the step portion.